求助嘛，有会verilog的大神吗帮忙看看仿真为啥出问题
实现一个两个输入地址两个输出数据的寄存器，代码放下面，给了一些注释。verilog仿真出来两个输出的rdata都是0，不知道是design文件出了问题还是testbench出了问题，有好心的大佬能不能帮忙看看？谢谢！！design文件：
`define DATA_WIDTH 32
`define ADDR_WIDTH 5
module reg_file(
input clk,
input rst,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr1,
input [`ADDR_WIDTH - 1:0] raddr2,
input wen,
input [`DATA_WIDTH - 1:0] wdata,
output [`DATA_WIDTH - 1:0] rdata1,
output [`DATA_WIDTH - 1:0] rdata2
);
integer i;
reg r;
initial
for(i=0; i<5; i=i+1)
r <= 0;
always @ (posedge clk)
begin
if(rst)
for(i=0; i<5; i=i+1)
r <= 0;
else
if(wen)
if(waddr != 0)
r <= wdata;
else
r <= 0;
end
assign rdata1 = r;
assign rdata2 = r;
endmodule
testbench文件：
`define DATA_WIDTH 32
`define ADDR_WIDTH 5
module reg_file_tb();
reg clk;
reg rst;
reg [`ADDR_WIDTH - 1:0] waddr;
reg wen;
reg [`DATA_WIDTH - 1:0] wdata;
reg [`ADDR_WIDTH - 1:0] raddr1;
reg [`ADDR_WIDTH - 1:0] raddr2;
wire [`DATA_WIDTH - 1:0] rdata1;
wire [`DATA_WIDTH - 1:0] rdata2;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
wen = 1;
end
initial begin
waddr = 1;
#5waddr = 2;
#5waddr = 3;
#5waddr = 4;
#5waddr = 0;
end
initial begin
wdata = 132;
#5wdata = 189;
#5wdata = 2;
#5wdata = 65;
#5wdata = 233;
end
initial begin
raddr1 = 0;
#5raddr1 = 1;
#5raddr1 = 2;
#5raddr1 = 3;
#5raddr1 = 4;
end
initial begin
raddr2 = 1;
#5raddr2 = 2;
#5raddr2 = 3;
#5raddr2 = 4;
#5raddr2 = 0;
end
reg_file u_reg_file(
.clk(clk),
.rst(rst),
.waddr(waddr),
.raddr1(raddr1),
.raddr2(raddr2),
.wen(wen),
.wdata(wdata),
.rdata1(rdata1),
.rdata2(rdata2)
);
endmodule
（简单起见只随便列了几个状态，将就着看看~） 已解决...rst初值一直赋的1...是我傻了
Shaky_00 发表于 2020-3-8 11:39
已解决...rst初值一直赋的1...是我傻了
竟然在鱼c问verilog 我也来学verilog了{:10_266:}
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