FPGA:流水灯
本帖最后由 划句顾 于 2023-2-4 20:56 编辑编译软件为Quartus II
语言:Verilog
注意:文件名和实体名要一致
一、以1秒为间隔,逐个点亮LED
/*
Time:2022/11/08
author:LaoGu
function:以1秒为间隔,逐个点亮LED;
*/
module LED(clk,rst,led);
input clk,rst;
output led;
reg LED_OUT;
reg cnt;
parameter max =26'd49_999_999; //50M次就是1s
reg flag;
//计时
always @(posedge clk,negedge rst) begin
if(!rst)
cnt = 0;
else if(cnt==max)
cnt = 0;
else
cnt = cnt + 1;
end
//1s标志
always @(posedge clk,negedge rst) begin
if(!rst)
flag = 0;
else if(cnt==max)
flag = 1;
else
flag = 0;
end
//LED 的变化
always @(posedge clk,negedge rst) begin
if(!rst)
LED_OUT <= 4'b0001;
else if(flag)begin
LED_OUT <= LED_OUT << 1;
LED_OUT <= LED_OUT;
end
end
assign led = LED_OUT;
endmodule
注:不要忘记引脚的设定。
static/image/hrline/5.gif
二、花样流水灯
方法一:用状态记录
/*
Time:2022/11/08
author:LaoGu
function:以1秒为间隔,逐个点亮LED,等LED全亮后,以1s依次熄灭。
*/
module LED(clk,rst,led);
//输入输出
input clk,rst;
output led;
//变量
reg LED_OUT;
reg cnt;
parameter max =26'd49_999_999;
reg flag;//1s标志
integer state; //LED状态标志
//时间
always @(posedge clk,negedge rst) begin
if(!rst)
cnt = 0;
else if(cnt==max)
cnt = 0;
else
cnt = cnt + 1;
end
//时间标志
always @(posedge clk,negedge rst) begin
if(!rst)
flag = 0;
else if(cnt==max)
flag = 1;
else
flag = 0;
end
//状态标志
always @(posedge clk,negedge rst) begin
if(!rst)
state = 1;
else if(flag)
begin
if(state == 7)
state = 1;
else
state = state + 1;
end
end
//LED的值变化
always @(posedge clk,negedge rst) begin
if(!rst)
LED_OUT = 4'b0001;
else if(flag)begin
if(state == 1) LED_OUT = 4'b0001;
else if(state == 2)LED_OUT = 4'b0011;
else if(state == 3)LED_OUT = 4'b0111;
else if(state == 4)LED_OUT = 4'b1111;
else if(state == 5)LED_OUT = 4'b0111;
else if(state == 6)LED_OUT = 4'b0011;
else if(state == 7)LED_OUT = 4'b0001;
else if(state == 8)LED_OUT = 4'b0000;
end
end
assign led = LED_OUT;
endmodule
static/image/hrline/5.gif
方法二:用数组
给数组赋值要在初始化那里赋值,也就是在
if(!rst) 这里面赋值
/*
Time:2022/11/15
author:LaoGu
function:用数组做一个花样流水灯
*/
module real_HY(clk,rst,led);
input clk,rst;
output reg led; //led在always里面,需要加定义的时候需要加reg
reg cnt;
parameter max =26'd49_999_999;
reg flag;
//定义数组
reg n ;//第一个【3:0】相当于char,后面的【3:0】相当于数组的个数
integer i;
//数组
always @(posedge clk,negedge rst) begin
if(!rst) begin//数组初始化
n= 4'b1001;
n= 4'b0110;
n= 4'b1010;
n= 4'b0101;
end
else if(i==3 && flag)
i = 0;
else if(flag)
i = i + 1;
end
//时间
always @(posedge clk,negedge rst) begin
if(!rst)
cnt = 0;
else if(cnt==max)
cnt = 0;
else
cnt = cnt + 1;
end
//时间标志
always @(posedge clk,negedge rst) begin
if(!rst)
flag = 0;
else if(cnt==max)
flag = 1;
else
flag = 0;
end
//给LED赋值
always @(posedge clk,negedge rst) begin
if(!rst)
led = n;
else if(flag)begin
led = n;
end
end
endmodule
三、流水灯实现左右流转
/*
Time:2022/11/15
author:LaoGu
function:使用dir作为方向变换的标志
*/
module led_bh(clk,rst,led);
//输入输出
input clk,rst;
output reg led;
//变量
reg cnt;
parameter max =26'd49_999_999;
reg flag;//1s标志
reg dir;
//时间
always @(posedge clk,negedge rst) begin
if(!rst)
cnt = 0;
else if(cnt==max)
cnt = 0;
else
cnt = cnt + 1;
end
//时间标志
always @(posedge clk,negedge rst) begin
if(!rst)
flag = 0;
else if(cnt==max)
flag = 1;
else
flag = 0;
end
//LED的值变化
always @(posedge clk,negedge rst) begin
if(!rst) begin
dir = 0;
led = 4'b0001;
end
else if(flag && !dir)begin
if(led == 4'b1000)
dir =1;
else
led = led << 1;
end
else if (flag && dir)begin
if(led == 4'b0001)
dir =0;
else
led = led >> 1;
end
end
endmodule
static/image/hrline/5.gif
这两个LED赋值方式是一样的效果
①//LED的值变化
always @(posedge clk,negedge rst) begin
if(!rst) begin
dir = 0;
led = 4'b0001;
end
else if(flag && !dir)begin
if(led == 4'b1000)
dir =1;
else
led = led << 1;
end
else if (flag && dir)begin
if(led == 4'b0001)
dir =0;
else
led = led >> 1;
end
end
②//LED的值变化
always @(posedge clk,negedge rst) begin
if(!rst) begin
dir = 0;
led = 4'b0001;
end
else if(flag )begin
if(!dir)begin
if(led == 4'b1000)
dir =1;
else
led = led << 1;
end
else if (dir)begin
if(led == 4'b0001)
dir =0;
else
led = led >> 1;
end
end
end
本帖最后由 划句顾 于 2023-2-4 21:41 编辑
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